Verilog Basis – Part 1

As we mention before, we are using verilog language in programming the FPGA board. Therefore, we are looking to some basis of the modeling in verilog language. The example as below:

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Structural Modelling

module schematic1 (f,A,B,C)

input A,B,C;

output f;

assign f=(A&B)|C;

endmodule

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Behavioral Modelling

module DFF (Q,D,clk)

input D,clk;

output Q;

always@(posedge clk)

Q<=D

endmodule

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Conveyor Model – Reference

In developing our own conveyor, we are using a model as a reference. Below are those model pictures:

Conveyor – Modelling Part

This is a modelling part of the conveyor. We used Alibre software to develop the model. Basically this model is depends on our FPGA-based sorter machine system . There are two rejection part and a camera that have their function respectively. Our idea is to locate two different shape object that used rejection part to choose the right shape as sort them in the right place. Camera is the most important element that will capture the object and send the information through FPGA system then will process by the VHDL programming that will activate the respective rejection part to sort the object.

Gantt Chart

Gant Chart

This is our planning for the whole semester. It’s only applied for FYP 1 only. The Gantt Chart will guide us to complete our FYP 1 during this semester.

For the FYP 2 there will be a new Gantt Chart.